const_defs.h

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// This file is automatically generated. Modifications may be overwritten.
// TODO: Add file preamble
 
#pragma once
 
#include <cstdint>
 
namespace uvgv3cbitstream {
 
constexpr int64_t VPS_EXT_MIV = 2;
constexpr int64_t VPS_EXT_MIV_2 = 3;
constexpr int64_t VPS_EXT_PACKED = 1;
constexpr int64_t VPS_EXT_VDMC = 4;
 
enum APM {
  I_INTRA = 0,
  P_SKIP = 0,
  I_RAW = 1,
  P_MERGE = 1,
  I_EOM = 2,
  P_INTER = 2,
  P_INTRA = 3,
  P_RAW = 4,
  P_EOM = 5,
  I_END = 14,
  P_END = 14
};
 
enum ATH {
  P_TILE = 0,
  I_TILE = 1,
  SKIP_TILE = 2
};
 
enum ATI {
  ATTR_TEXTURE = 0,
  ATTR_MATERIAL_ID = 1,
  ATTR_TRANSPARENCY = 2,
  ATTR_REFLECTANCE = 3,
  ATTR_NORMAL = 4,
  ATTR_UNSPECIFIED = 15
};
 
enum CGI {
  AVC_Progressive_High = 0,
  HEVC_Main_10 = 1,
  HEVC_Main_4_4_4_10 = 2,
  VVC_Main_10 = 3,
  HEVC_Main = 4,
  MP4RA = 127
};
 
enum FPO {
  FPO_NULL = 0,
  FPO_MROT270 = 1,
  FPO_SWAP = 1,
  FPO_ROT90 = 2,
  FPO_ROT180 = 3,
  FPO_ROT270 = 4,
  FPO_MIRROR = 5,
  FPO_MROT90 = 6,
  FPO_MROT180 = 7
};
 
enum LI {
  Level_1_0 = 30,
  Level_1_1 = 33,
  Level_1_5 = 45,
  Level_2_0 = 60,
  Level_2_1 = 63,
  Level_2_2 = 66,
  Level_2_5 = 75,
  Level_3_0 = 90,
  Level_3_1 = 93,
  Level_3_2 = 96,
  Level_3_5 = 105,
  Level_4_0 = 120,
  Level_4_1 = 123,
  Level_4_2 = 126,
  Level_4_5 = 135,
  Level_8_5 = 255
};
 
enum MDI {
  max_1 = 0,
  max_2 = 1,
  max_3 = 2,
  max_4 = 3,
  max_6 = 4,
  max_12 = 5,
  max_16 = 6,
  max_24 = 7,
  max_32 = 8,
  unconstrained = 15
};
 
enum NAL {
  NAL_TRAIL_N = 0,
  NAL_TRAIL_R = 1,
  NAL_TSA_N = 2,
  NAL_TSA_R = 3,
  NAL_STSA_N = 4,
  NAL_STSA_R = 5,
  NAL_RADL_N = 6,
  NAL_RADL_R = 7,
  NAL_RASL_N = 8,
  NAL_RASL_R = 9,
  NAL_SKIP_N = 10,
  NAL_SKIP_R = 11,
  NAL_RSV_ACL_N12 = 12,
  NAL_RSV_ACL_R13 = 13,
  NAL_RSV_ACL_N14 = 14,
  NAL_RSV_ACL_R15 = 15,
  NAL_BLA_W_LP = 16,
  NAL_BLA_W_RADL = 17,
  NAL_BLA_N_LP = 18,
  NAL_GBLA_W_LP = 19,
  NAL_GBLA_W_RADL = 20,
  NAL_GBLA_N_LP = 21,
  NAL_IDR_W_RADL = 22,
  NAL_IDR_N_LP = 23,
  NAL_GIDR_W_RADL = 24,
  NAL_GIDR_N_LP = 25,
  NAL_CRA = 26,
  NAL_GCRA = 27,
  NAL_RSV_IRAP_ACL_28 = 28,
  NAL_RSV_IRAP_ACL_29 = 29,
  NAL_RSV_ACL_30 = 30,
  NAL_RSV_ACL_31 = 31,
  NAL_RSV_ACL_32 = 32,
  NAL_RSV_ACL_33 = 33,
  NAL_RSV_ACL_34 = 34,
  NAL_RSV_ACL_35 = 35,
  NAL_ASPS = 36,
  NAL_AFPS = 37,
  NAL_AUD = 38,
  NAL_V3C_AUD = 39,
  NAL_EOS = 40,
  NAL_EOB = 41,
  NAL_FD = 42,
  NAL_PREFIX_NSEI = 43,
  NAL_SUFFIX_NSEI = 44,
  NAL_PREFIX_ESEI = 45,
  NAL_SUFFIX_ESEI = 46,
  NAL_AAPS = 47,
  NAL_CASPS = 48,
  NAL_CAF_IDR = 49,
  NAL_CAF_TRAIL = 50,
  NAL_RSV_NACL_51 = 51,
  NAL_RSV_NACL_52 = 52,
  NAL_RSV_NACL_53 = 53,
  NAL_RSV_NACL_54 = 54,
  NAL_RSV_NACL_55 = 55,
  NAL_UNSPEC_56 = 56,
  NAL_UNSPEC_57 = 57,
  NAL_UNSPEC_58 = 58,
  NAL_UNSPEC_59 = 59,
  NAL_UNSPEC_60 = 60,
  NAL_UNSPEC_61 = 61,
  NAL_UNSPEC_62 = 62,
  NAL_UNSPEC_63 = 63
};
 
enum TSI {
  V_PCC_Basic = 0,
  V_PCC_Extended = 1,
  MIV_Main = 64,
  MIV_Extended = 65,
  MIV_Geometry_Absent = 66,
  MIV_2 = 67,
  MIV_Simple_MPI = 68
};
 
enum VUT {
  V3C_VPS = 0,
  V3C_AD = 1,
  V3C_OVD = 2,
  V3C_GVD = 3,
  V3C_AVD = 4,
  V3C_PVD = 5,
  V3C_CAD = 6,
  V3C_BMD = 7,
  V3C_ADD = 8
};
 
} // namespace uvgv3cbitstream